1. Field of the Invention
This invention relates to optimizing heat-transfer in 3-D chip-stacks. More particularly, this invention relates to optimizing heat-transfer in 3-D chips stacks using a heuristic approach.
2. Related Art
Three-dimensional integrated circuits are prevalent in today's semiconductor industry because they address and overcome several technical shortcomings. For instance, 3-D packaging, which involves stacking several chips into a single package, provides at least a partial remedy to the scaling obstacles presented by two dimensional alternatives.
Nevertheless, one problem presented by Three-dimensional stacks (“3-D chip-stacks”) is that the proximity amongst the stacked layers can cause temperature variations that either damage the layers, or components therein, or make the layers, or components therein, operate improperly. For instance, “hot spots” can occur in certain areas of the chip, which can dramatically impede performance, and even permanently damage the chip.
The methods and systems for addressing the temperature and flow variations in 3-D chip-stacks are flawed for a variety of reasons, including lacking the ability of adequately eliminating hot-spots throughout the chip-stack, and for not being versatile enough to address the temperature and flow needs at particular portions of the 3-D chip-stack without compromising the needs of other portions of the chip-stack (which in turn affects the performance of the chip-stack as a whole).
Consequently, a need has developed to address the concerns presented by this problem.